Scan Insertion at the Behavioral Level

Improving testability of complex designs through DFT (Design-For-Testability) has been widely investigated for several years. Designers are taking fully advantage of silicon compilers that allow a design to be synthesized given its behavioral description. However, test logic is still considered only once the logic synthesis is accomplished. This does not take fully advantage of the optimization that is permitted through synthesis. Furthermore, handling DFT at low level is heavy when dealing with complex designs and needs from designers technical expertise on testing.